Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An important step in the manufacture of ICs such as PLDs is testing microchips prior to shipment to a customer. Presently, testing is performed by applying input stimuli in the form of test vectors to inputs of the device under test (DUT). The test vectors are typically strings of binary digits designed to exercise desired circuitry within the PLD. During the test, output of the DUT is recorded and compared with expected output for the test vectors. Conventionally, engineers create test vectors by hand by setting each bit in the vectors. Such manual creation of test vectors is time consuming and error prone. Accordingly, there exists a need in the art for an improved method and apparatus for generating vectors for an integrated circuit under test.
In addition, the ability to verify an IC design is also an important part of the design process. Each IC design in a logic type device must be simulated to insure that the logic performs as designed. Engineers currently divide a complete IC into sections by circuit and then create simulation vectors by hand for each component of the circuitry. This is time consuming and error prone, but this is a required step in order to insure quality and prevent costly repair of the IC device. Accordingly, there exists a need in the art to provide an automated approach to simulate the entire IC.